1. Field of the Invention:
The present invention relates to a semiconductor memory device fabricated on a semiconductor chip.
2. Description of the Related Art:
In a conventional semiconductor memory, a memory cell array is divided to a plurality of sub-arrays so as to increase the memory capacity without causing a decrease of the operation speed and an increase of the power consumption. Especially, in a recently-developed semiconductor memory in which a large memory capacity and a high-speed operation are required, the memory cell array is divided into a plurality of sub-arrays with respect to the directions of word lines or digit lines in some cases. For example, in a 256 K bits dynamic memory, memory cells of 256 K bits are divided into four sub-arrays each having memory cells of 64 K bits and each of the sub-arrays is provided with a row decoder for selecting one of rows of the associated sub-array.
In order to operate the respective row decoders provided for the respective sub-arrays, it is necessary to supply a plurality of address signals to the respective row decoders from an adders buffers. For example, in the case where each of the row decoders receives N-bits of address signals, N-bits of true and complementary address signals are derived from the address buffer and transmitted to the respective row decoders via an address bus composed of 2N address wirings extending along the sub-arrays. The address wirings usually extending in the longitudinal direction of the semiconductor chip and have large lengths. Therefore, the address wirings occupy a relatively large area on the semiconductor chip, and such a large area is a large obstacle to increase the memory capacity and integration density. Moreover, the address wirings themselves have large stray capacitances due to their large lengths. As is well known in the art, all of the address wirings are precharged before an active operation and half of the address wirings are discharged in the active operation. Therefore, a relatively large electric charges are consumed through the precharge and discharge operations of the address wirings.
As explained above, the conventional memory device has large drawbacks that the address wirings occupy a large chip area and consume a large electric current.